DIFFERENT FPGA PRODUCTS BASED IMPLEMENTATION OF LTE TURBO CODE

Abstract

In the long-term evolution (LTE) physical layer, using turbo code is considered as the paramount one in error-correcting coding. This paper presents an implementation of LTE turbo decoding using the Log- Maximum a posteriori (MAP) algorithm with reduced number of required cycles approximately by 75% based on serial to parallel operation. Also an improvement for this algorithm based on polynomial regression function to reduce the implementation complexity. All this system implementation design with 40 bit block size of the input using Xilinx System Generator (XSG). This system implementation in hardware to show its applicability in real time using two approaches; Hardware Co-Simulation and HDL Netlist based on three devices, Xilinx Kintex-7, Spartan-6 and Artix-7. Observe from the hardware implementation, the system become completely real time by controlled from the user using the switches on the board. Also, this system taken the resources utilization from the devices less than other works.